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general description the max5590?ax5595 octal, 12/10/8-bit, voltage-out- put digital-to-analog converters (dacs) offer buffered outputs and a 3? maximum settling time at the 12-bit level. the dacs operate from a +2.7v to +5.25v analog supply and a separate +1.8v to +5.25v digital supply. the 20mhz 3-wire serial interface is compatible with spi, qspi, microwire, and digital signal processor (dsp) protocol applications. multiple devices can share a common serial interface in direct-access or daisy-chained configuration. the max5590?ax5595 provide two multifunction, user-programmable, digital i/o ports. the externally selectable power-up states of the dac outputs are either zero scale, midscale, or full scale. software-selectable fast and slow settling modes decrease settling time in fast mode, or reduce supply current in slow mode. the max5590/max5591 are 12-bit dacs, the max5592/ max5593 are 10-bit dacs, and the max5594/ max5595 are 8-bit dacs. the max5590/max5592/ max5594 provide unity-gain-configured output buffers, while the max5591/max5593/max5595 provide force- sense-configured output buffers. the max5590 max5595 are specified over the extended -40? to +85? temperature range, and are available in space- saving 24-pin and 28-pin tssop packages. applications portable instrumentation automatic test equipment (ate) digital offset and gain adjustment automatic tuning programmable voltage and current sources programmable attenuators industrial process controls motion control microprocessor (?)-controlled systems power amplifier control fast parallel-dac to serial-dac upgrades features ? octal, 12/10/8-bit serial dacs in tssop packages ? 3? (max) 12-bit settling time to 1/2 lsb ? integral nonlinearity: 1 lsb (max) max5590/max5591 a-g rade (12-bit) 1 lsb (max) max5592/max5593 (10-bit) 1/2 lsb (max) max5594/max5595 (8-bit) ? guaranteed monotonic, ? lsb (max) dnl ? two user-programmable digital i/o ports ? single +2.7v to +5.25v analog supply ? +1.8v to av dd digital supply ? 20mhz, 3-wire, spi-/qspi-/microwire-/dsp- compatible serial interface ? glitch-free outputs power up to zero scale, midscale, or full scale controlled by pu pin ? unity-gain or force-sense-configured output buffers max5590?ax5595 buffered, fast-settling, octal, 12/10/8-bit, v oltage-output dacs ________________________________________________________________ maxim integrated products 1 ordering information 19-2983; rev 0; 9/03 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. * future product?ontact factory for availability. specifications are preliminary. selector guide and pin configurations appear at end of data sheet. spi/qspi are trademarks of motorola, inc. microwire is a trademark of national semiconductor corp. part temp range pin-package max5590 aeug* -40 c to +85 c 24 tssop MAX5590BEUG -40 c to +85 c 24 tssop max5591 aeui* -40 c to +85 c 28 tssop max5591beui -40 c to +85 c 28 tssop max5592 eug -40 c to +85 c 24 tssop max5593 eui -40 c to +85 c 28 tssop max5594 eug -40 c to +85 c 24 tssop max5595 eui -40 c to +85 c 28 tssop
max5590emax5595 buffered, fast-settling, octal, 12/10/8-bit, v oltage-output dacs 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (av dd = 2.7v to 5.25v, dv dd = 1.8v to av dd , agnd = 0, dgnd = 0, v ref = 2.5v (for av dd = 2.7v to 5.25v), v ref = 4.096v (for av dd = 4.5v to 5.25v), r l = 10k , c l = 100pf, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 c.) (note 1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. av dd to dv dd ........................................................................6v agnd to dgnd ..................................................................0.3v av dd to agnd, dgnd.............................................-0.3v to +6v dv dd to agnd, dgnd ............................................-0.3v to +6v fb_, out_, ref to agnd ........-0.3v to the lower of (av dd + 0.3v) or +6v sclk, din, cs p dsp dnd 0 d dd 0 pi1 pi dnd 0 d dd 0 m c a p 0a c p d t a 0 c p tssp 1 c 0 c p tssp 1 c 0 c 10 t r 0 c c s t r c 10 c m t 10 c l t 10 00 c parameter sml cnditins min tp ma nits static accrac ma0ma1 1 mama 10 r n mama ma0ama1a 1 1 ma0ma1 1 mama 10 0 1 i n inl ref a dd ref 0 a dd n mama 01 0 ls d n dnl n 1 ls m a 0am a 1a 1 0 m a 0m a 1 1 0 mama 10 10 e s mama e d fs c ma0ama1a 1 ma0ma0 1 0 0 mama 10 10 e e f mama ls e d 1 fs c
max5590emax5595 buffered, fast-settling, octal, 12/10/8-bit, v oltage-output dacs _______________________________________________________________________________________ 3 electrical characteristics (continued) (av dd = 2.7v to 5.25v, dv dd = 1.8v to av dd , agnd = 0, dgnd = 0, v ref = 2.5v (for av dd = 2.7v to 5.25v), v ref = 4.096v (for av dd = 4.5v to 5.25v), r l = 10k , c l = 100pf, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 c.) (note 1) parameter symbol conditions min typ max units power-supply rejection ratio psrr full-scale output, av dd = 2.7v to 5.25v 200 v/v reference input reference input range v ref 0.25 av dd v reference input resistance r ref normal operation (no code dependence) 145 200 k reference leakage current shutdown mode 0.5 1 a dac output characteristics unity gain 85 slow mode, full scale force sense 67 unity gain 140 output voltage noise fast mode, full scale force sense 110 v rms unity-gain output 0 av dd output voltage range (note 3) force-sense output 0 av dd / 2 v dc output impedance 38 av dd = 5v, out_ to agnd, full scale, fast mode 57 short-circuit current av dd = 3v, out_ to agnd, full scale, fast mode 45 ma power-up time from v dd applied until interface is functional 30 60 s wake-up time coming out of shutdown, outputs settled 40 s output out_ and fb_ open-circuit leakage current programmed in shutdown mode, force-sense outputs only 0.01 a digital outputs (upio_) output high voltage v oh i source = 2ma dv dd - 0.5 v output low voltage v ol i sink = 2ma 0.4 v digital inputs (sclk, cs di dsp pi d dd i i d dd d dd d dd d dd i l il d dd i l c i i a i c c i f
max5590emax5595 buffered, fast-settling, octal, 12/10/8-bit, v oltage-output dacs 4 _______________________________________________________________________________________ electrical characteristics (continued) (av dd = 2.7v to 5.25v, dv dd = 1.8v to av dd , agnd = 0, dgnd = 0, v ref = 2.5v (for av dd = 2.7v to 5.25v), v ref = 4.096v (for av dd = 4.5v to 5.25v), r l = 10k , c l = 100pf, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 c.) (note 1) parameter symbol conditions min typ max units pu input input high voltage v ih-pu dv dd - 200mv v input low voltage v il-pu 200 mv input leakage current i in-pu pu still considered floating when connected to a tri-state bus 200 na dynamic performance fast mode 3.6 voltage-output slew rate sr slow mode 1.6 v/s m ax 5590/m ax 5591 fr om cod e 322 to cod e 4095 to 1/2 ls b 23 m ax 5 592/m ax 5 593 fr om cod e 10 to cod e 10 23 to 1/2 ls b 1.5 3 fast mode max5594/max5595 fr om cod e 3 to code 255 to 1/2 lsb 12 m ax 5590/m ax 5591 fr om cod e 322 to cod e 4095 to 1/2 ls b 36 max5592/max5593 fr om cod e 10 to code 1023 1/2 lsb 2.5 6 voltage-output settling time (note 5) slow mode max5594/max5595 fr om cod e 3 to code 255 to 1/2 lsb 24 s fb_ input voltage 0 v ref / 2 v fb_ input current 0.1 a unity gain 200 reference -3db bandwidth (note 6) force sense 150 khz digital feedthrough cs d dd 0 d dd d dd 0 100h 01 da i m dacdac c n 1
max5590emax5595 buffered, fast-settling, octal, 12/10/8-bit, v oltage-output dacs _______________________________________________________________________________________ 5 electrical characteristics (continued) (av dd = 2.7v to 5.25v, dv dd = 1.8v to av dd , agnd = 0, dgnd = 0, v ref = 2.5v (for av dd = 2.7v to 5.25v), v ref = 4.096v (for av dd = 4.5v to 5.25v), r l = 10k , c l = 100pf, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 c.) (note 1) parameter symbol conditions min typ max units power requirements analog supply voltage range av dd 2.70 5.25 v digital supply voltage range dv dd 1.8 av dd v unity gain 1.5 3.2 slow mode, all digital inputs at dgnd or dv dd , no load, v ref = 4.096v force sense 2.4 4.8 unity gain 2.5 8 operating supply current i avdd + i dvdd fast mode, all digital inputs at dgnd or dv dd , no load, v ref = 4.096v force sense 3.4 8 ma shutdown supply current i av d d ( s h d n ) + i d v d d ( s h d n ) no clocks, all digital inputs at dgnd or dv dd , all dacs in shutdown mode 0.5 1 a note 1: for the force-sense versions, fb_ is connected to its respective out_. v out (max) = v ref / 2, unless otherwise noted. note 2: linearity guaranteed from decimal code 40 to code 4095 for the max5590b/max5591b (12-bit, b-grade), code 10 to code 1023 for the max5592/max5593 (10-bit), and code 3 to code 255 for the max5594/max5595 (8-bit). note 3: represents the functional range. the linearity is guaranteed at v ref = 2.5v (for av dd from 2.7v to 5.25v), and v ref = 4.096v (for av dd = 4.5v to 5.25v). see the typical operating characteristics section for linearity at other voltages. note 4: dc crosstalk is measured as follows: outputs of dacaedach are set to full scale and the output of dach is measured. while keeping dach unchanged, the outputs of dacaedacg are transitioned to zero scale and the v out of dach is measured. note 5: guaranteed by design. note 6: the reference -3db bandwidth is measured with a 0.1v p-p sine wave on v ref and with full-scale input code.
max5590emax5595 buffered, fast-settling, octal, 12/10/8-bit, v oltage-output dacs 6 _______________________________________________________________________________________ timing characteristics?dsp mode disabled (3v, 3.3v, 5v logic) (figure 1) (dv dd = 2.7v to 5.25v, gnd = 0, t a = t min to t max , unless otherwise noted.) parameter symbol conditions min typ max units sclk frequency f sclk 2.7v < dv dd < 5.25v 20 mhz sclk pulse-width high t ch (note 7) 20 ns sclk pulse-width low t cl (note 7) 20 ns cs f sclk r s t css 10 sclk r cs r h t csh sclk r cs f s cs0 10 din sclk r s t ds 1 din sclk r h t dh sclk r dtdc1 p d d1 c l 0f pi dtdc1 0 sclk f dt p d d c l 0f pi dtdc0 dtr 0 cs r sclk r h t cs1 micrire spi 0 10 cs p h cs pi timin characteristics dt ts t e dtdc0 dtdc1 pi m d c l 0f pi 100 dtr ts t cs r dr c l 0f cs pi 0 dtr ts e t sclk r en c l 0f sclk pi 0 ldac p l ldl f 0 ldac e d lds f 100 clr mid set p l cms f 0 p s t p f 100 p hi t p 100
max5590emax5595 buffered, fast-settling, octal, 12/10/8-bit, v oltage-output dacs _______________________________________________________________________________________ 7 timing characteristics?dsp mode disabled (1.8v logic) (figure 1) (dv dd = 1.8v to 5.25v, gnd = 0, t a = t min to t max , unless otherwise noted.) parameter symbol conditions min typ max units sclk frequency f sclk 1.8v < dv dd < 5.25v 10 mhz sclk pulse-width high t ch (note 7) 40 ns sclk pulse-width low t cl (note 7) 40 ns cs f sclk r s t css 0 sclk r cs r h t csh 0 sclk r cs f s cs0 10 din sclk r s t ds 0 din sclk r h t dh sclk r dtdc1 p d d1 c l 0f pi dtdc1 0 sclk f dt p d d c l 0f pi dtdc0 dtr 0 cs r sclk r h t cs1 micrire spi 0 0 cs p h cs 0 pi timin characteristics dt ts t e dtdc0 dtdc1 pi m d c l 0f pi 00 dtr ts t cs r dr c l 0f cs pi 0 dtr ts e t sclk r en c l 0f sclk pi 0 ldac p l ldl f 0 ldac e d lds f 00 clr mid set p l cms f 0 p s t p f 00 p hi t p 00
max5590emax5595 buffered, fast-settling, octal, 12/10/8-bit, v oltage-output dacs 8 _______________________________________________________________________________________ timing characteristics?dsp mode enabled (3v, 3.3v, 5v logic) (figure 2) (dv dd = 2.7v to 5.25v, gnd = 0, t a = t min to t max , unless otherwise noted.) parameter symbol conditions min typ max units sclk frequency f sclk 2.7v < dv dd < 5.25v 20 mhz sclk pulse-width high t ch (note 7) 20 ns sclk pulse-width low t cl (note 7) 20 ns cs f sclk f s t css 10 dsp f sclk f s t dss 10 sclk f cs r h t csh sclk f cs f d cs0 10 sclk f dsp f d ds0 10 din sclk f s t ds 1 din sclk f h t dh sclk r dt p d d1 c l 0f pi dtdc1 dtr 0 sclk f dt p d d c l 0f pi dtdc0 0 cs r sclk f h t cs1 micrire spi 0 10 cs p h cs dsp p h ds 0 dsp p l dspl n 0 pi timin characteristics dt ts t e dtdc0 dtdc1 pi m d c l 0f pi 100 dtr ts t cs r dr c l 0f cs pi 0 dtr ts e t sclk f en c l 0f sclk pi 0 ldac p l ldl f 0 ldac e d lds f 100 clr mid set p l cms f 0 p s t p f 100 p hi t p 100
max5590emax5595 buffered, fast-settling, octal, 12/10/8-bit, v oltage-output dacs _______________________________________________________________________________________ 9 timing characteristics?dsp mode enabled (1.8v logic) (figure 2) (dv dd = 1.8v to 5.25v, gnd = 0, t a = t min to t max , unless otherwise noted.) parameter symbol conditions min typ max units sclk frequency f sclk 1.8v < dv dd < 5.25v 10 mhz sclk pulse-width high t ch (note 7) 40 ns sclk pulse-width low t cl (note 7) 40 ns cs f sclk f s t css 0 dsp f sclk f s t dss 0 sclk f cs r h t csh 0 sclk f cs f d cs0 10 sclk f dsp f d ds0 1 din sclk f s t ds 0 din sclk f h t dh sclk r dt p d d1 c l 0f pi dtdc1 dtr 0 sclk f dt p d d c l 0f pi dtdc0 0 cs r sclk f h t cs1 micrire spi 0 0 cs p h cs 0 dsp p h ds 0 dsp p l dspl n 0 pi timin characteristics dt ts t e dtdc0 dtdc1 pi m d c l 0f pi 00 dtr ts t cs r dr c l 0f cs pi 0 dtr ts e t sclk f en c l 0f sclk pi 0 ldac p l ldl f 0 ldac e d lds f 00 clr mid set p l cms f 0 p s t p f 00 p hi t p 00 n i i 1 0 1 n t dsp dsp cs dsp cs 10 0 1 cs
max5590emax5595 buffered, fast-settling, octal, 12/10/8-bit, v oltage-output dacs 10 ______________________________________________________________________________________ -4 -2 -3 -1 0 1 2 3 4 0 1024 2048 3072 4095 integral nonlinearity vs. digital input code (12-bit) max5590-95 toc01 digital input code inl (lsb) b-grade -1.00 -0.50 -0.75 -0.25 0 0.25 0.50 0.75 1.00 02 56 512 768 1023 integral nonlinearity vs. digital input code (10-bit) max5590-95 toc02 digital input code inl (lsb) -0.50 -0.25 0 0.25 0.50 064 128 192 255 integral nonlinearity vs. digital input code (8-bit) max5590-95 toc03 digital input code inl (lsb) -0.50 -0.25 0 0.25 0.50 0 1024 2048 3072 4095 differential nonlinearity vs. digital input code (12-bit) max5590-95 toc04 digital input code dnl (lsb) b-grade -0.2 -0.1 0 0.1 0.2 0256 512 768 1023 differential nonlinearity vs. digital input code (10-bit) max5590-95 toc05 digital input code dnl (lsb) -0.050 -0.025 0 0.025 0.050 064128 192 255 differential nonlinearity vs. digital input code (8-bit) max5590-95 toc06 digital input code dnl (lsb) -4 -2 -3 0 -1 1 2 3 4 1.0 2.0 2.5 1.5 3.0 3.5 4.0 4.5 5.0 integral nonlinearity vs. reference voltage (12-bit) max5590-95 toc07 v ref (v) inl (lsb) b-grade midscale -0.5 -0.3 -0.4 -0.1 -0.2 0.1 0 0.2 0.4 0.3 0.5 1.0 20 2.5 1.5 3.0 3.5 4.0 4.5 5.0 differential nonlinearity vs. reference voltage (12-bit) max5590-95 toc08 v ref (v) dnl (lsb) b-grade midscale -4 0 -2 -3 -1 2 4 3 1 -40 10 -15 35 60 85 integral nonlinearity vs. temperature (12-bit) max5590-95 toc09 temperature ( c) inl (lsb) b-grade midscale t ypical operating characteristics (av dd = dv dd = 5v, v ref = 4.096v, r l = 10k , c l = 100pf, speed mode = fast, pu = floating, t a = +25 c, unless otherwise noted.)
max5590emax5595 buffered, fast-settling, octal, 12/10/8-bit, v oltage-output dacs ______________________________________________________________________________________ 11 -0.2 0 -0.1 0.1 0.2 -40 10 -15 35 60 85 differential nonlinearity vs. temperature (12-bit) max5590-95 toc10 temperature ( c) dnl (lsb) b-grade midscale 0 1 2 3 4 5 01 024 2048 3072 4095 supply current vs. digital input code (force-sense) max5590-95 toc11 digital input code supply current (ma) 12-bit no load 0 1 2 3 01 024 2048 3072 4095 supply current vs. digital input code (unity gain) max5590-95 toc12 digital input code supply current (ma) 12-bit no load 0 1 2 3 4 2.70 3.40 4.10 4.80 5.25 supply current vs. supply voltage (force-sense) max5590-95 toc13 supply voltage (v) supply current (ma) slow mode f ast mode av dd = dv dd no load 0 0.5 1.0 1.5 2.0 2.5 3.0 2.70 3.40 4.10 4.80 5.25 supply current vs. supply voltage (unity gain) max5590-95 toc14 supply voltage (v) supply current (ma) av dd = dv dd no load slow mode f ast mode 0 20 10 30 50 40 60 2.70 4.10 3.40 4.80 5.25 shutdown supply current vs. supply voltage max5590-95 toc15 supply voltage (v) shutdown supply current (na) no load force sense unity gain 0 1 2 4 5 3 6 7 -40 10 -15 35 60 85 offset error vs. temperature max5590-95 toc16 temperature ( c) offset error (lsb) code = 40 unity gain: 1 lsb = 1mv force sense : 1 lsb = 0.5mv unity gain force sense -10 -8 -4 -6 -2 0 -40 10 -15 35 60 85 gain error vs. temperature max5590-95 toc17 temperature ( c) gain error (lsb) force sense unity gain unity gain: 1 lsb = 1mv force sense : 1 lsb = 0.5mv 0 0.5 1.5 1.0 2.0 2.5 -15 -5 -10 0 5 10 15 output voltage vs. output source/sink current max5590-95 toc18 i out (ma) output voltage (v) unity gain v ref = 4.096v midscale t ypical operating characteristics (continued) (av dd = dv dd = 5v, v ref = 4.096v, r l = 10k , c l = 100pf, speed mode = fast, pu = floating, t a = +25 c, unless otherwise noted.)
max5590emax5595 buffered, fast-settling, octal, 12/10/8-bit, v oltage-output dacs 12 ______________________________________________________________________________________ major-carry transition glitch max5590-95 toc19 250ns/div out_ 2mv/div cs 5v/div settling time positive max5590-95 toc20 400ns/div out_ 2v/div cs 5v/div full-scale transition settling time negative max5590-95 toc21 400ns/div out_ 2v/div cs 5v/div full-scale transition 5 -25 1 100 1000 10 10,000 reference input bandwidth max5590-95 toc22 frequency (khz) gain (db) -20 -15 -10 -5 0 v ref = 0.1v p-p at 4.096v dc unity gain reference feedthrough at 1khz max5590-95 toc23 frequency (khz) signal amplitude (db) 5.0 4.5 3.5 4.0 1.5 2.0 2.5 3.0 1.0 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -22 -142 0.5 5.5 200 s/div dac-to-dac crosstalk outh 1mv/div outa?utg 2v/div max5590-95 toc24 t ypical operating characteristics (continued) (av dd = dv dd = 5v, v ref = 4.096v, r l = 10k , c l = 100pf, speed mode = fast, pu = floating, t a = +25 c, unless otherwise noted.) 1 s/div digital feedthrough out_ (ac-coupled) 2mv/div sclk 2v/div max5590-95 toc25 400 s/div power-up glitch out_ 2v/div av dd 2v/div max5590-95 toc26 pu = dv dd 10 s/div exiting shutdown to midscale out_ 2v/div cs 2v/div max5590-95 toc27
max5590emax5595 buffered, fast-settling, octal, 12/10/8-bit, v oltage-output dacs ______________________________________________________________________________________ 13 pin description pin max5590 max5592 max5594 max5591 max5593 max5595 name function 11 av dd analog supply 22 agnd analog ground 33 outa daca output 4, 8, 17, 21 ? n.c. no connection. not internally connected. 56 outb dacb output 67 outc dacc output 710 outd dacd output 911 cs al cs i 10 1 sclk s c i 11 1 din s d i 1 1 dsp c e c dsp d dd sclk c dsp nd sclk c dsp dnd sclk 1 1 d dd d s 1 1 dnd d 1 1 pi1 p i 1 1 1 pi p i 1 1 te dace 1 tf dacf 0 t dac th dach p p s s i c p d dd tath c p dnd tath l p tath ref r i fa f daca f f dac fc f dacc fd f dacd 0 fe f dace 1 ff f dacf f f dac fh f dach
max5590emax5595 buffered, fast-settling, octal, 12/10/8-bit, v oltage-output dacs 14 ______________________________________________________________________________________ functional diagrams max5590 max5592 max5594 dout register 16-bit shift register cs sclk din dsp serial interface control mux av dd upio1 upio2 ref pu upio1 and upio2 logic power-down logic and register decode control input register a dac register a daca outa input register h dach outh dac register h dv dd agnd dgnd
max5590emax5595 buffered, fast-settling, octal, 12/10/8-bit, v oltage-output dacs ______________________________________________________________________________________ 15 functional diagrams (continued) max5591 max5593 max5595 dout register 16-bit shift register cs sclk din dsp serial interface control mux av dd upio1 upio2 ref pu upio1 and upio2 logic power-down logic and register decode control input register a dac register a daca outa fba fbh input register h dach outh dac register h dv dd agnd dgnd
max5590emax5595 buffered, fast-settling, octal, 12/10/8-bit, v oltage-output dacs 16 ______________________________________________________________________________________ detailed description the max5590emax5595 octal, 12/10/8-bit, voltage-out- put dacs offer buffered outputs and a 3s maximum settling time at the 12-bit level. the dacs operate from a single 2.7v to 5.25v analog supply and a separate 1.8v to av dd digital supply. the max5590emax5595 include an input register and dac register for each channel and a 16-bit data-in/data-out shift register. the 3-wire serial interface is compatible with spi, qspi, microwire, and dsp applications. the max5590e max5595 provide two user-programmable digital i/o ports, which are pro- grammed through the serial interface. the externally selectable power-up states of the dac outputs are either zero scale, midscale, or full scale. reference input the reference input, ref, accepts both ac and dc val- ues with a voltage range extending from analog ground (agnd) to av dd . the voltage at ref sets the full-scale output of the dacs. determine the output voltage using the following equations: unity-gain versions: v out_ = (v ref x code) / 2 n force-sense versions (fb_ connected to out_): v out = 0.5 x (v ref x code) / 2 n where code is the numeric value of the dac?s binary input code and n is the bits of resolution. for the max5590/max5591, n = 12 and code ranges from 0 to 4095. for the max5592/max5593, n = 10 and code ranges from 0 to 1023. for the max5594/ max5595, n = 8 and code ranges from 0 to 255. output buffers the daca and dach output-buffer amplifiers of the max5590emax5595 are unity-gain stable with rail-to- rail output voltage swings and a typical slew rate of 3.6v/s (fast mode). the max5590/max5592/ max5594 provide unity-gain outputs, while the max5591/max5593/max5595 provide force-sense out- puts. for the max5591/max5593/max5595, access to the output amplifier?s inverting input provides flexibility in output gain setting and signal conditioning (see the applications information section). the max5590emax5595 offer fast and slow settling- time modes. in the slow mode, the settling time is 6s (max), and the supply current is 3.2ma (max). in the fast mode, the settling time is 3s (max), and the sup- ply current is 8ma (max). see the digital interface section for settling-time mode programming details. use the serial interface to set the shutdown output impedance of the amplifiers to 1k or 100k for the max5590/max5592/max5594 and 1k or high imped- ance for the max5591/max5593/max5595. the dac outputs can drive a 10k (typ) load and are stable with up to 500pf (typ) of capacitive load. power-on reset at power-up, all dac outputs power up to full scale, midscale, or zero scale, depending on the configuration of the pu input. connect pu to dv dd to set out_ to full scale upon power-up. connect pu to digital ground (dgnd) at power-up to set out_ to zero scale. leave pu floating to set out_ to midscale. digital interface the max5590emax5595 use a 3-wire serial interface that is compatible with spi, qspi, microwire, and dsp protocol applications (figures 1 and 2). connect dsp d dd sclk c dsp dnd sclk a dsp dsp r ma0ma p h t ma0ma 1 t t 1 1 cs 1 t ms f ma0ma1 1 cc0 1 d11d0 t 1 f 10 ma ma d11d d1 d0 f ma ma d11d dd0 s e dac dac a dac p t dac l dac dac dac rr n m l
max5590emax5595 buffered, fast-settling, octal, 12/10/8-bit, v oltage-output dacs ______________________________________________________________________________________ 17 table 1. serial write data format msb 16 bits of serial data lsb control bits data bits c3 c2 c1 c0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 figure 1. serial-interface timing diagram (dsp mode disabled) figure 2. serial-interface timing diagram (dsp mode enabled) sclk din cs doutdc1* doutdc0 or doutrb* *upio1/upio2 configured as doutdc_ (daisy-chain data output, mode 0 or 1) or doutrb (read-back data output). see the data output (doutrb, doutdc0, doutdc1) section for details. t ch t ds t cs0 t dh t csh t do1 t do2 t cl t csw t cs1 dout valid dout valid t css c1 d0 c2 c3 sclk din cs dsp doutdc0* doutdc1 or doutrb* *upio1/upio2 configured as doutdc_ (daisy-chain data output, mode 0 or 1) or doutrb (read-back data output). see the data output (doutrb, doutdc0, doutdc1) section for details. t cl t ds t ccs t dsw t dspwl t d02 t d01 t dh t cs0 t ch c3 c2 c1 d0 t csh t csw t dss t cs1 t ds0 dout valid dout valid
max5590emax5595 buffered, fast-settling, octal, 12/10/8-bit, v oltage-output dacs 18 ______________________________________________________________________________________ sclk din c3 c2 c1 c0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 din sclk dv dd command takes effect here only if sclk count = n 16 command takes effect here only if sclk count = n 16 microwire or spi (cpol = 0, cpha = 0) 8-bit control data or 12-bit dac data write: cs must remain low between bytes on a 16-bit write operation spi (cpol = 1, cpha = 1) 8-bit control data or 12-bit dac data write: cs must remain low between bytes on a 16-bit write operation din sclk cs cs max5590 max5595 v dd v dd microwire sk so i/o sclk din dv dd max5590 max5595 v dd v dd spi or qspi sck mosi ss or i/o cs dsp dsp cs c3 c2 c1 c0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 sclk din c3 c2 c1 c0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 c3 c2 c1 c0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 din sclk dgnd command takes effect here only if sclk count = n 16 command takes effect here only if sclk count = n 16 dsp or spi (cpol = 0, cpha = 0) 8-bit control data or 12-bit dac data write: dsp or spi (cpol = 1, cpha = 0) 8-bit control data or 12-bit dac data write: din sclk cs cs max5590 max5595 v ss dsp tclk, sclk, or clkx dt or dx tfs or fsx sclk din dgnd max5590 max5595 v ss spi or qspi sck mosi ss or i/o cs dsp dsp cs cs must remain low between bytes on a 16-bit write operation cs must remain low between bytes on a 16-bit write operation figure 3. microwire and spi single dac writes (cpol = 0, cpha = 0 or cpol = 1, cpha = 1) figure 4. dsp and spi single dac writes (cpol = 0, cpha = 1 or cpol = 1, cpha = 0) serial-interface programming commands tables 2a, 2b, and 2c provide all of the serial-interface programming commands for the max5590?ax5595. table 2a shows the basic dac programming com- mands, table 2b gives the advanced-feature program- ming commands, and table 2c provides the 24-bit read commands. figures 3 and 4 provide the serial- interface diagrams for read and write operations. loading input and dac registers the max5590?ax5595 contain a 16-bit shift register that is followed by a 12-bit input register and a 12-bit dac register for each channel (see the functional diagrams ). tables 3, 4, and 5 highlight a few of the commands that handle the loading of the input and dac registers. see table 2a for all dac programming commands.
max5590emax5595 buffered, fast-settling, octal, 12/10/8-bit, v oltage-output dacs ______________________________________________________________________________________ 19 control bits data bits d a t a c3 c2 c1 c0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 function input registers (aeh) din 0000d11d10d9 d8 d7 d6 d5 d4 d 3/0 d 2/0 d 1/0 d 0/0 load input register a from shift register; dac registers are unchanged. dac outputs are unchanged.* din 0001d11d10d9 d8 d7 d6 d5 d4 d 3/0 d 2/0 d 1/0 d 0/0 load input register b from shift register; dac registers are unchanged. dac outputs are unchanged.* din 0010d11d10d9 d8 d7 d6 d5 d4 d 3/0 d 2/0 d 1/0 d 0/0 load input register c from shift register; dac registers are unchanged. dac outputs are unchanged.* din 0011d11d10d9 d8 d7 d6 d5 d4 d 3/0 d 2/0 d 1/0 d 0/0 load input register d from shift register; dac registers are unchanged. dac outputs are unchanged.* din 0100d11d10d9 d8 d7 d6 d5 d4 d 3/0 d 2/0 d 1/0 d 0/0 load input register e from shift register; dac registers are unchanged. dac outputs are unchanged.* din 0101d11d10d9 d8 d7 d6 d5 d4 d 3/0 d 2/0 d 1/0 d 0/0 load input register f from shift register; dac registers are unchanged. dac outputs are unchanged.* din 0110d11d10d9 d8 d7 d6 d5 d4 d 3/0 d 2/0 d 1/0 d 0/0 load input register g from shift register; dac registers are unchanged. dac outputs are unchanged.* din 0111d11d10d9 d8 d7 d6 d5 d4 d 3/0 d 2/0 d 1/0 d 0/0 load input register h from shift register; dac registers are unchanged. dac outputs are unchanged.* table 2a. dac programming commands * for the max5592/max5593 (10-bit version), d11ed2 are the significant bits and d1 and d0 are sub-bits. for the max5594/max5595 ( 8-bit version), d11ed4 are the significant bits and d3ed0 are sub-bits. set all sub-bits to zero during the write commands.
max5590emax5595 buffered, fast-settling, octal, 12/10/8-bit, v oltage-output dacs 20 ______________________________________________________________________________________ control bits data bits data c3 c2 c1 c0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 function select bits di n 1000 xxxx mh mg mf me md mc mb ma load d ac r eg i ster _ fr om i np ut r eg i ster _ w hen m _ = 1. d ac r eg i ster _ i s unchang ed i f m _ = 0. loading input and dac registers (aeh) di n 1001 d11 d10 d9 d8 d7 d6 d5 d4 d3/0 d2/0 d1/0 d0/0 load all input registers aeh from their respective shift registers; dac registers are unchanged. dac outputs are unchanged.* di n 1010 d11 d10 d9 d8 d7 d6 d5 d4 d3/0 d2/0 d1/0 d0/0 load all input and dac registers aeh from their respective shift registers. dac outputs updated. shutdown bits di n 10110000 pdd1 pdd0 pdc1 pdc0 pdb1 pdb0 pda1 pda0 write dacaedacd shutdown-mode bits. see table 8. di n 10110001 xxxxxxxx doutrb xxxxxxxx pdd1 pdd0 pdc1 pdc0 pdb1 pdb0 pda1 pda0 read-back dacaedacd shutdown-mode bits. di n 10110010 pdh1 pdh0 pdg1 pdg0 pdf1 pdf0 pde1 pde0 write daceedach shutdown-mode bits. see table 8. di n 10110011 xxxxxxxx doutrb xxxxxxxx pdh1 pdh0 pdg1 pdg0 pdf1 pdf0 pde1 pde0 read-back daceedach shutdown-mode bits. di n 10110100 pdch pdcg pdcf pdce pdcd pdcc pdcb pdca write dac shutdown- control bits. di n 10110101 xxxxxxxx doutrb xxxxxxxx pdch pdcg pdcf pdce pdcd pdcc pdcb pdca read-back dac shutdown-control settings. table 2b. advanced-feature programming commands x = don?t care. * for the max5592/max5593 (10-bit version), d11ed2 are the significant bits and d1 and d0 are sub-bits. for the max5594/max5595 ( 8-bit version), d11ed4 are the significant bits and d3ed0 are sub-bits. set all sub-bits to zero during the write commands.
max5590emax5595 buffered, fast-settling, octal, 12/10/8-bit, v oltage-output dacs ______________________________________________________________________________________ 21 control bits data bits data c3 c2 c1 c0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 function upio configuration bits di n 10110110 u p s l2 u p s l1 u p 3u p 2u p 1u p 0 x x wr i te u p io confi g ur ati on b i ts. s ee tab l es 19 and 22. din 10110111x x x x x x x x doutrb x x x x x x x x u p 3- 2u p 2- 2u p 1- 2u p 0- 2u p 3- 1u p 2- 1u p 1- 1u p 0- 1 read - b ack u p io confi g ur ati on b i ts functi on. settling-time-mode bits di n 10111000 s p d h s p d gs p d fs p d e s p d d s p d c s p d bs p d a wr i te settl i ng - ti m e b i ts for d ac aed ac h ( 0 = s low [ d ef aul t, 6s] , 1 = fas t [ 3s] ) . din 10111001x x x x x x x x doutrb x x x x x x x x s p d h s p d gs p d fs p d e s p d d s p d c s p d bs p d a read - b ack d ac settl i ng - ti m e b i ts. upio_ as gpi (general-purpose input) di n 1011101xxx x xxx x x doutrb xx x xxx x xxx rtp2 lf2 lr2 rtp1 lf1 lr1 read u p io _ i np uts ( val i d onl y w hen u p io1 or u p io2 i s confi g ur ed as a g e ner al - p ur p ose i np ut.) s ee the gp i, gp ol, gp oh secti on. cpol and cpha control bits din 11000000x x x x x x c p o lc p h a wr i te c p o l, c p h a c ontr ol b i ts. s ee tab l e 15. din 11000001x x x x x x x x doutrb x x x x x x x x x x x x x x c p o lc p h a read c p ol, c p h a contr ol b i ts. table 2b. advanced-feature programming commands (continued) x = don?t care.
max5590emax5595 buffered, fast-settling, octal, 12/10/8-bit, v oltage-output dacs 22 ______________________________________________________________________________________ control bits data bits data c3 c2 c1 c0 d27 d26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 function read input and dac registers aeh din 1 101 0 0 0 x 1 111111111111111xxxxxxxx doutrb x xxx x x x x dda_11 dda_10 dda_9 dda_8 dda_7 dda_6 dda_5 dda_4 dda_3 dda_2 dda_1 dda_0 ida_11 ida_10 ida_9 ida_8 ida_7 ida_6 ida_5 ida_4 ida_3 ida_2 ida_1 ida_0 read input register a and dac register a (all 24 bits).** ? ? ? ? ? ? ? ? ? during readback, all ones (code ff) must be clocked into din for all 24 bits. no command can be issued before all 24 bits have been clocked out. cs
max5590emax5595 buffered, fast-settling, octal, 12/10/8-bit, v oltage-output dacs ______________________________________________________________________________________ 23 dac programming examples: to load input register a from the shift register, leaving dac register a unchanged (dac output unchanged), use the command in table 3. the max5590emax5595 can load all of the input regis- ters (aeh) simultaneously from the shift register, leaving the dac registers unchanged (dac output unchanged), by using the command in table 4. to load all of the input registers (aeh) and all of the dac registers (aeh) simultaneously, use the command in table 5. for the 10-bit and 8-bit versions, set sub-bits = 0 for best performance. advanced-feature programming commands select bits (m_) the select bits allow synchronous updating of any com- bination of channels. the select bits command the loading of the dac register from the input register of each channel. set the select bit m_ = 1 to load the dac register _ with data from the input register _, where _ is replaced with a, b, or c and so on through h, depending on the selected channel. setting the select bit m_ = 0 results in no action for that channel (table 6). select bits programming example: to load dac register b from input register b while keeping other channels (a, ceh) unchanged, set mb = 1 and m_ = 0 (table 7). table 3. load input register a from shift register table 4. load input registers (aeh) from shift register table 5. load input registers (aeh) and dac registers (aeh) from shift register table 6. select bits (m_) data control bits data bits din 0000 d11 d10 d9 d8 d7 d6 d5 d4 d3/0 d2/0 d1/0 d0/0 data control bits data bits din 1 0 0 1 d11 d10 d9 d8 d7 d6 d5 d4 d3/0 d2/0 d1/0 d0/0 data control bits data bits din 1 0 1 0 d11 d10 d9 d8 d7 d6 d5 d4 d3/0 d2/0 d1/0 d0/0 data control bits data bits din 1 0 00xxxxmhmgmfmemdmcmbma table 7. select bits programming example data control bits data bits din 1000 xx0000 000010 x = don?t care. x = don?t care.
max5590emax5595 buffered, fast-settling, octal, 12/10/8-bit, v oltage-output dacs 24 ______________________________________________________________________________________ table 9. shutdown-mode write command (dacaedacd) table 10. shutdown-mode write command (daceedach) table 11. shutdown-control-bits write command data control bits data bits din 10110000 p d d 1p d d 0p d c 1p d c 0p d b1 p d b0 p d a1 p d a0 data control bits data bits din 1 0 1 10010p d h 1p d h 0p d g 1p d g 0p d f1 p d f0 p d e 1p d e 0 data control bits data bits di n 10110100p d c h p d c gp d c fp d c e p d c d p d c c p d c bp d c a x = don?t care. x = don?t care. table 12. settling-time-mode write command data control bits data bits din 10111000 s p d h s p d gs p d fs p d e s p d d s p d c s p d b s p d a x = don?t care. shutdown-mode bits (pd_0, pd_1) use the shutdown-mode bits and control bits to shut down each dac independently. the shutdown- mode bits determine the output state of the selected channels. the shutdown-control bits put the selected channels into shutdown-mode. to select the shutdown mode for dacaedach, set pd_0 and pd_1 according to table 8 (where _ is replaced with one of the select- ed channels (aeh)). the three possible states for unity- gain versions are 1) normal operation, 2) shutdown with 1k output impedance, and 3) shutdown with 100k output impedance. the three possible states for force- sense versions are 1) normal operation, 2) shutdown with 1k output impedance, and 3) shutdown with the output in a high-impedance state. tables 9 and 10 show the commands for writing to the shutdown-mode bits. table 11 shows the commands for writing the shutdown-control bits. this command is required to put the selected channels into shutdown. always write the shutdown-mode-bits command first and then write the shutdown-control-bits command to properly shut down the selected channels. the shut- down-control-bits command can be written at any time after the shutdown-mode-bits command. it does not have to immediately follow the shutdown-mode-bits command. settling-time-mode bits (spd_) the settling-time-mode bits select the settling time (fast mode or slow mode) of the max5590emax5595. set spd_ = 1 to select fast mode or set spd_ = 0 to select slow mode, where _ is replaced by a, b, or c and so on through h, depending on the selected chan- nel (table 12). fast mode provides a 3s maximum set- tling time, and slow mode provides a 6s maximum settling time. table 8. shutdown-mode bits pd_1 pd_0 descriptions 00 shutdown with 1k termination to ground on dac_ output. 01 shutdown with 100k termination to ground on dac_ output for unity-gain versions. shutdown with high-impedance output for force-sense versions. 10 ignored. 11 dac_ is powered up in its normal operating mode.
max5590emax5595 buffered, fast-settling, octal, 12/10/8-bit, v oltage-output dacs ______________________________________________________________________________________ 25 settling-time-mode write example: to configure daca and dacd into fast mode and dacb and dacc into slow mode, use the command in table 13. to read back the settling-time-mode bits, use the com- mand in table 14. cpol and cpha control bits the cpol and cpha control bits of the max5590emax5595 are defined the same as the cpol and cpha bits in the spi standard. set the dac?s cpol and cpha bits to cpol = 0 and cpha = 0 or cpol = 1 and cpha = 1 for microwire and spi applications requiring the clocking of data in on the ris- ing edge of sclk. set the dac?s cpol and cpha bits to cpol = 0 and cpha = 1 or cpol = 1 and cpha = 0 for dsp and spi applications, requiring the clocking of data in on the falling edge of sclk (refer to the programmer?s handbook and see table 15 for details). at power-up, if dsp d dd cpha dsp dnd cpha t cpl t cpl cpha t 1 t cpl cpha t 1 t 1 stm e data cntrl its data its din 101110001001 d t 1 stm r c data cntrl its data its din 1 0 1 11001 d tr s p d h s p d s p d fs p d e s p d d s p d c s p d s p d a t 1 cpl cpha r c data cntrl its data its din 1 1 0 0 0 0 0 1 d tr c p l c p h a t 1 cpl cpha cpl cpha descriptin 00 d dsp d dd d sclk 01 d dsp dnd d sclk 10 d sclk 11 d sclk t 1 cpl cpha c data cntrl its data its din 11000000 c p l c p h a d d d
max5590emax5595 buffered, fast-settling, octal, 12/10/8-bit, v oltage-output dacs 26 ______________________________________________________________________________________ table 20. upio programming example data control bits data bits din 10110110010000xx x = don?t care. table 21. upio read command data control bits data bits di n1 0 110111 xxxxxxxx doutrb xxxxxxxx u p 3- 2u p 2- 2u p 1- 2u p 0- 2u p 3- 1u p 2- 1u p 1- 1 u p 0- 1 x = don?t care. upio bits (upsl1, upsl2, up0eup3) the max5590emax5595 provide two user-programma- ble input/output (upio) ports: upio1 and upio2. these ports have 15 possible configurations, as shown in table 22. upio1 and upio2 can be programmed inde- pendently or simultaneously by writing to the upsl1, upsl2, and up0eup3 bits (table 18). table 19 shows how upio1 and upio2 are selected for configuration. the up0eup3 bits select the desired functions for upio1 and/or upio2 (table 22). upio programming example: to set only upio1 as ldac pi t 0 t pi ma0ma pi1 pi dtr t 1 pi t 1 pi t p p0 pp0 pi t p1 p01 pp0 pi1 t 1 pi c data cntrl its data its din 10110110 p s l p s l1 p p p1 p0 d t 1 pi s psl1 psl psl psl1 pi prt selected 00 n 01 pi1 10 pi 11 pi1 pi
max5590emax5595 buffered, fast-settling, octal, 12/10/8-bit, v oltage-output dacs ______________________________________________________________________________________ 27 upio configuration table 22 lists the possible configurations for upio1 and upio2. upio1 and upio2 use the selected function when configured by the up3eup0 configuration bits. ldac ldac dac ldac dac dac dac ldac dac dac dac d ldac dac dac t ldac cs sclk din i ldac cs dac ldac 10 cs t dac s f t pi c r pp0 pi cnfiratin its p p p1 p0 fnctin descriptin 0000 ldac al l dac i d dac 0001 set al i d dac 0010 mid al i d dac 0011 clr al i d dac 0100 pdl al pd l i d 0101 r t d 0110 shdn1k al 1 s i pd1 pd0 f ma0mama shdn1k tath and 1 f ma1mama shdn1k tath 0111 shdn100k al 100 s i pd1 pd0 f ma0mama shdn100k tath and 100 f ma1mama tath 1000 dtr d r 1001 dtdc0 m 0 dc d d 1010 dtdc1 m 1 dc d d sclk 1011 pi p l i 1100 pl p ll 1101 ph p lh 1110 t t i t dac dac d dac d dac dac 1111 fast fs stm i d fast sl spdaspdh
max5590emax5595 buffered, fast-settling, octal, 12/10/8-bit, v oltage-output dacs 28 ______________________________________________________________________________________ set mid clr t set mid clr dac f t t set dac set set dac dac t mid dac mid mid dac dac t clr dac clr clr dac dac i clr mid set pd l pdl t pdl pd0 pd1 pdl shdn1k shdn100k s m shdn1k shdn100k i pd0 pd1 dac pdl dac pdl pd0 pd1 s m s s h h d d n n 1 1 k k s s h h d d n n 1 1 0 0 0 0 k k shdn1k shdn100k pd1 pd0 f ma0mama shdn1k ta th 1 shdn100k 100 f ma1ma ma shdn1k 1 shdn100k f t t d dtr dtdc0 dtdc1 pi1 pi dtr dtdc0 0 dtdc1 1 t dtr dtdc0 dtdc1 t dtr dt d dtdc r dtr dac d dtdc dac 1 t dtr cs d dtdc s f 1 t gp t lds end of cycle* gpo_ ldac * end-of-cycle represents the rising edge of cs or the 16th active clock edge, depending on the mode of operation. t cms t ldl t s 0.5 lsb togg v out_ ldac pdl clr, mid, or set pdl affects dac ouptuts (v out_ ) only if dacs were previously shut down. figure 5. asynchronous signal timing figure 6. gpo_ and ldac s t
max5590emax5595 buffered, fast-settling, octal, 12/10/8-bit, v oltage-output dacs ______________________________________________________________________________________ 29 gpi, gpol, gpoh upio1 and upio2 can each be configured as a gener- al-purpose input (gpi), a general-purpose output low (gpol), or a general-purpose output high (gpoh). the gpi can serve to detect interrupts from ps or micro- controllers. the gpi has three functions: 1) sample the signal at gpi at the time of the read (rtp1 and rtp2). 2) detect whether or not a falling edge has occurred since the last read or reset (lf1 and lf2). 3) detect whether or not a rising edge has occurred since the last read or reset (lr1 and lr2). rtp1, lf1, and lr1 represent the data read from upio1; rtp2, lf2, and lr2 represent the data read from upio2. to issue a read command for the upio configured as gpi, use the command in table 23. once the command is issued, rtp1 and rtp2 provide the real-time status (0 or 1) of the inputs at upio1 or upio2, respectively, at the time of the read. if lf2 or lf1 is one, then a falling edge has occurred on the respective upio1 or upio2 input since the last read or reset. if lr2 or lr1 is one, then a rising edge has occurred since the last read or reset. gpol outputs a constant low, and gpoh outputs a constant high. see figure 6. togg use the togg input to toggle the dac outputs between the values in the input registers and dac reg- isters. a delay of greater than 100ns from the end of the previous write command is required before the togg signal can be correctly switched between the new value and the previously stored value. when togg = 0, the output follows the information in the input regis- ters. when togg = 1, the output follows the informa- tion in the dac register (figure 5). fast t mama fast sl t fast fast sl fast t spdaspdh t pi r c data cntrl its data its di n1 0 11101 dtr rtp lf lr rtp1 lf1 lr1 t c t 1 dac cntents ms ls anal tpt 1111 1111 1111 ref 0 0 1000 0000 0001 ref 0 0 1000 0000 0000 ref 0 0 ref 0111 1111 1111 ref 0 0 0000 0000 0001 ref 1 0 0000 0000 0000 0 max5590 dac_ ref_ out_ v out_ = v ref_ x code / 4096 code is the dac_ input code (0 to 4095 decimal). figure 7. unipolar output circuit x = don? care.
max5590emax5595 buffered, fast-settling, octal, 12/10/8-bit, v oltage-output dacs 30 ______________________________________________________________________________________ applications information unipolar output figure 7 shows the unity-gain max5590 in a unipolar output configuration. table 24 lists the unipolar out- put codes. bipolar output the max5590 outputs can be configured for bipolar operation, as shown in figure 8. the output voltage is given by the following equation: v out_ = v ref x (code - 2048) / 2048 where code represents the numeric value of the dac?s binary input code (0 to 4095 decimal). table 25 shows digital codes and the corresponding output volt- age for the figure 8 circuit. configurable output gain the max5591/max5593/max5595 have force-sense outputs, which provide a direct connection to the invert- ing terminal of the output op amp, yielding the most flexibility. the force-sense output has the advantage that specific gains can be set externally for a given application. the gain error for the max5591/max5593/ max5595 is specified in a unity-gain configuration (op- amp output and inverting terminals connected), and additional gain error results from external resistor tolerances. the force-sense dacs allow many useful circuits to be created with only a few simple external components. an example of a custom, fixed gain using the max5591?s force-sense output is shown in figure 9. in this example, the external reference is set to 1.25v, and the gain is set to +1.1v/v with external discrete resis- tors to provide an approximate 0 to 1.375v dac output voltage range. v out = [(0.5 x v ref_ x code) / 4096] x [1 + (r2 / r1)] where code represents the numeric value of the dac?s binary input code (0 to 4095 decimal). in this example, r2 = 12k and r1 = 10k to set the gain = 1.1v/v. v out = [(0.5 x 1.25v x code) / 4096] x 2.2 table 25. bipolar code table (gain = +1) dac contents msb lsb analog output 1111 1111 1111 +v ref (2047 / 2048) 1000 0000 0001 +v ref (1 / 2048) 1000 0000 0000 0 0111 1111 1111 -v ref (1 / 2048) 0000 0000 0001 -v ref (2047 / 2048) 0000 0000 0000 -v ref (2048 / 2048) = -v ref figure 8. bipolar output circuit max5590 dac_ ref out_ 10k 10k v+ v- v out max5591 dac_ ref out_ fb_ r2 = 12k 0.1% 25ppm r1 = 10k 0.1% 25ppm figure 9. configurable output gain
max5590emax5595 buffered, fast-settling, octal, 12/10/8-bit, v oltage-output dacs ______________________________________________________________________________________ 31 power-supply and layout considerations bypass the analog and digital power supplies by using a 10f capacitor in parallel with a 0.1f capacitor to agnd and dgnd (figure 10). minimize lead lengths to reduce lead inductance. use shielding and/or ferrite beads to fur- ther increase isolation. digital and ac transient signals coupling to agnd can create noise at the output. connect agnd to the high- est quality ground available. use proper grounding techniques, such as a multilayer board with a low- inductance ground plane. wire-wrapped boards and sockets are not recommended. for optimum system performance, use pc boards with separate analog and digital ground planes. connect the two ground planes together at the low-impedance power-supply source. using separate power supplies for av dd and dv dd improves noise immunity. connect agnd and dgnd at the low-impedance power-supply sources (figure 11). max5590?ax5595 v ref 10 f* 0.1 f* ref sclk din pu upio1 upio2 cs dsp agnd** dgnd** outa fba fbh outh max5591 max5593 max5595 only 10 f 0.1 f 10 f 0.1 f dv dd av dd dv dd av dd *remove bypass capacitors on ref for ac-reference inputs. **connect analog and digital ground planes at the low-impedance power-supply source. figure 10. bypassing power supplies av dd , dv dd , and ref max5590?ax5595 0.1 f 10 f av dd agnd av dd agnd 0.1 f 10 f dv dd dgnd dv dd dgnd dv dd dgnd analog supply digital supply digital circuitry figure 11. separate analog and digital power supplies
max5590emax5595 buffered, fast-settling, octal, 12/10/8-bit, v oltage-output dacs 32 ______________________________________________________________________________________ chip information transistor count: 38,513 process: bicmos 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 ref pu outh n.c. n.c. outa agnd av dd top view outg outf oute n.c. n.c. outd outc outb 16 15 14 13 9 10 11 12 upio2 upio1 dgnd dv dd dsp din sclk cs tssop max5590 max5592 max5594 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 ref pu outh fbh fbg outg dv dd outf fbf fbe oute upio2 upio1 dgnd dsp din sclk cs outd fbd fbc outc outb fbb fba outa agnd av dd tssop max5591 max5593 max5595 pin configurations selector guide part output buffer co nfigur ation r eso l u tio n ( b it s) inl ( lsbs max) max5590aeug* unity gain 12 ? MAX5590BEUG unity gain 12 ? max5591aeui* force sense 12 ? max5591beui force sense 12 ? max5592eug unity gain 10 ? max5593eui force sense 10 ? max5594eug unity gain 8 ?.5 max5595eui force sense 8 ?.5 * future product. contact factory for availability. specifications are preliminary.
max5590emax5595 buffered, fast-settling, octal, 12/10/8-bit, v oltage-output dacs maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 33 ? 2003 maxim integrated products printed usa is a registered trademark of maxim integrated products. package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .) tssop4.40mm.eps

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